FinFET - A Three-Dimensional Transistor

[ABS News Service/07.03.2022]

For decades, the IC industry has incorporated the traditional planar transistor in chip designs, but this technology is running out of gas at the 20nm logic node. This is due to short-channel effects and other factors. So to circumvent these issues, the industry is moving towards finFET transistors. Intel moved into production with finFETs at the 22nm node. The foundries ramped up finFETs at 16nm/14nm.

In finFETs, the traditional 2D planar gate is replaced with a silicon fin that rises up vertically from the silicon substrate. The control of current is accomplished by implementing a gate on each of the three sides of the fin–two on each side and one across the top. FinFET transistors, in turn, form conducting channels on three sides of a fin structure, providing a fully depleted operation. This enables chips to operate at lower voltage at lower leakage.

Generally, a finFET could have two to four fins in the same structure. The spacing between the individual fins is the fin pitch. Chipmakers hope to scale the fin pitch by 0.7X at each node. The lithography process determines the fin pitch.

Meanwhile, each fin has a distinct width, height and shape. The fins are developed using deposition, etch and other steps. And, of course, the gate also has various characteristics, namely the gate length.

In one finFET production flow, the substrate initially goes through various lithography steps, namely spacer-based patterning. In this process, spacer-like structures are patterned on the substrate. Then, between these structures, an etcher carves out vertical trenches down into the substrate, thereby forming fins. After that, the spaces are filled with oxide using a deposition process. The top portion is polished and then the device undergoes a recess etch step. Finally, a gate oxide is deposited, followed by the formation of the gate