Semiconductor Industry Giants and Top Software Companies Create the Universal
Chiplet Interconnect Express Consortium
[ABS News Service/04.03.2022]
Advanced Semiconductor Engineering (ASE), AMD, Arm, Google
Cloud, Intel Corporation, Meta, Microsoft Corporation, Qualcomm Incorporated, Samsung,
and Taiwan Semiconductor Manufacturing Company today announce the formation of the
UCIe industry consortium that will establish a die-to-die
interconnect standard and foster an open chiplet ecosystem.
Leading processor makers such as AMD, Arm, Intel, Qualcomm, Samsung, as
well as TSMC and
ASE Group, together with giants like Google Cloud, Meta and
Microsoft are
establishing the Universal Chiplet Interconnect Express
(UCIe) consortium to facilitate the creation of a chiplet ecosystem and accelerate the adoption of future chiplet technologies. The consortium representing diverse market
segments will address customer requests for more customizable package-level integration,
connecting best-in-class die-to-die interconnect and protocols from an interoperable,
multi-vendor ecosystem.
The founding companies ratified the first version of UCIe specifications as an open industry standard developed to
establish a ubiquitous interconnect at the package level. The UCIe 1.0 spec sheet covers the die-to-die
I/O physical layer, die-to-die protocols, and software stack which leverage the
well-established PCI Express (PCIe) and Compute Express
Link (CXL) industry standards. As pointed out by Anandtech,
this initial version of UCIe comes from Intel, who is
donating the specification wholesale to the consortium. Not at all surprising, considering
that Intel has been responsible for the initial development of several high-profile
open interconnect technologies like USB, PCIe and Thunderbolt 3 over
the last two decades. As such, UCIe 1.0 is actually based
on Intel’s Advanced Interface Bus designs.
Upon incorporation of the new UCIe
industry organization later this year, member companies will begin work on the next
generation of UCIe technology, including defining the
chiplet form factor, management, enhanced security, and
other essential protocols.