Huawei
Faces US Restrictions with LogicFolding Architecture
to Boost Kirin 2026 Chip Performance Without Advanced Lithography
The chip is set to power the Mate
handset and will use Huawei’s Tau Scaling Law framework, which drastically
shortens distance that signals travel in circuit
·
Huawei has revealed production data
showing that its upcoming Kirin 2026 smartphone processor delivers
significant performance gains without using a more advanced semiconductor
process node or extreme ultraviolet (EUV) lithography.
·
The improvements are driven by Huawei's new LogicFolding architecture, detailed in an
updated paper on the company's proposed Tau Scaling Law, authored by He
Tingbo, Chairwoman of Huawei's Scientist
Committee and President of its Semiconductor Business Department.
·
The Kirin 2026 achieves a 55% increase in
transistor density compared with the Kirin 9030 Pro, despite both
chips being manufactured using the same process node.
·
According to Huawei, achieving a similar density
improvement through conventional Moore's Law transistor scaling would
normally require about three years of process-node shrinkage.
·
Instead of reducing transistor size, LogicFolding improves chip performance through topological
reorganisation of logic circuits, optimising the spatial arrangement of
transistors.
·
Operating at 25°C and 0.9 volts, the Kirin
2026:
o
reduces power consumption by 41% while
maintaining the same performance level as the Kirin 9030 Pro;
o
cuts power density by 5.6%,
improving energy efficiency.
·
Huawei's double-layer LogicFolding
architecture also:
o
reduces signal wire length by 30%;
o
cuts clock-buffer count by more than 50%;
and
o
lowers clock skew by 25%, improving signal
timing across the chip.
·
The production data provide the first engineering
evidence supporting Huawei's Tau Scaling Law, first introduced in May
2026, which proposes improving chip performance by accelerating data
movement rather than relying solely on smaller transistors.
·
Huawei claims that continued development of LogicFolding could enable transistor densities comparable
to a 1.4-nanometre process by 2031, without requiring EUV lithography
equipment, which China cannot import due to U.S. export restrictions.
·
The company expects LogicFolding
to evolve from local critical-path folding to full multi-layer
active-tier chip architectures with three, four or more active layers in a
package.
·
Huawei projects that the Kirin processor family
could increase CPU clock speeds from around 3.1 GHz in 2026 to
approximately 4.0 GHz by 2029 using this approach.
·
He Tingbo described the
proposed technology roadmap as technically feasible and economically viable.
·
However, analysts caution that commercial
deployment will require overcoming significant challenges, including:
o
heat dissipation,
o
manufacturing yield,
o
advanced packaging,
o
design toolchains, and
o
supply-chain constraints.
·
Huawei has called for industry-wide
collaboration to address these remaining technical bottlenecks, noting that
advances in design tools, standards, benchmarking, device physics and economic
models will require contributions from multiple organisations.
Huawei
Technologies’ coming smartphone processor is on track for a performance boost, without
the need for more advanced processing nodes or lithography technology, according
to new production data unveiled by the firm.
Using
Huawei’s LogicFolding architecture, the Kirin 2026, a
mobile processor set to power the firm’s coming flagship Mate handsets launching
this autumn, has increased transistor density by 55 per cent compared to last year’s
Kirin9030 Pro, according to an updated paper on the company’s Tau Scaling Law, initially
announced in May, by “chip queen” He Tingbo.
An
improvement in a single technological generation, achieved with the same process
node for the two Kirin chips, would have previously required three years of traditional
geometric scaling by shrinking the transistor size, according to the paper updated
last Friday.
The
gains were “obtained not through a new lithography step but through a topological
reorganisation of the spatial distribution of logic”, wrote He, who is chairwoman
of the Huawei Scientist Committee and president of the company’s semiconductor business
department.
Operating
at 25 degrees Celsius and 0.9V, the Kirin 2026 also reduced power consumption by
41 per cent to achieve the same level of performance as the Kirin9030 Pro baseline,
with a 5.6 per cent decrease in power density.
The
double-layer folding architecture has drastically shortened the distance that signals
travel by cutting wire length down by 30 per cent, reducing clock-buffer count by
over 50 per cent and clock skew by 25 per cent, the report said.
The
research, published on ChinaXiv, a publication platform
for scientific papers that have yet to be peer reviewed, gave the industry a glimpse
of the actual engineering details and production data after He presented the theoretical
framework of the Tau Scaling Law in late May.
Proposed
as an alternative to building smaller and smaller transistors under Moore’s Law
to boost chip performance, the Tau Scaling Law focuses on how fast data moves through
a system.
He
Tingbo, chairwoman of Huawei Scientist Committee and president
of the company’s semiconductor business department on May 25. Photo: Handout
With
the Tau law, Huawei claimed it could achieve transistor densities equivalent to
the cutting-edge 1.4-nanometre process by 2031 – all without the need for advanced
extreme ultraviolet lithography machines, which are banned for sale in China due
to US sanctions.
Key
to Huawei’s theory is a technology called LogicFolding
architecture, which can reduce the resistive and capacitive load of signal propagation,
ultimately boosting transistor density.
“Over
the next decade, LogicFolding is expected to evolve from
local critical-path folding to full-scale, multi-layer folding — three, four, and
more active tiers per package,” He wrote in her latest paper.
He
added that LogicFolding could enable the Kirin line to
substantially boost the CPU core frequency, a metric of how fast the chip can perform,
to 3.1 GHz this year and 4 GHz in 2029.
“The
road map is feasible and, in cost terms, economically viable,” He said.
However,
translating the theory into commercial reality would require overcoming a series
of supply chain chokepoints including heat dissipation and manufacturing yield,
according to analysts.
He
called on the industry to contribute to solving those bottlenecks of the Tau Scaling
Law.
“Many
open questions remain, and no single organisation can address them alone,” He wrote
in the paper. “The toolchain, the standards, the benchmarks, the device physics,
and the economic models all require contributions from beyond any one company.”