Six Pillar Semicon 2.0 Scheme Notified for Six Year Duration Covering Both Domestic and International
Companies, China Role Not Clarified
[MeitY Notification F. No.
W-38/6/2025-IPH dated 31 August 2026]
·
Semicon 2.0 has been
notified to provide sustained policy and fiscal support to Indias
semiconductor sector across the entire value chain, covering chip
design, fabrication, packaging and related ecosystem segments.
·
Core objective: Build a self-reliant and
globally competitive semiconductor ecosystem, strengthen supply-chain
resilience and national security, and establish technological leadership in
critical sectors.
Six
Pillars & 10 Categories
1.
Pillar 1 Design
o
Category 1: Semiconductor IPs, chips, SoCs
and modules for national importance and strategic priorities.
o
Category 2: Semiconductor IPs, chips and
SoCs for the commercial sector.
o
Category 3: Deployment-Linked Incentive
(DLI) for semiconductor IPs/chips/SoCs.
2.
Pillar 2 Machines & Materials
o
Category 4: Semiconductor manufacturing
ecosystem, including R&D facilities for semiconductor equipment,
semiconductor-grade raw materials, capital equipment, refurbished equipment,
components and testing/characterisation facilities.
3.
Pillar 3 Setting up More Fabs
o
Category 5: Silicon semiconductor wafer
fabs.
o
Category 6: Compound semiconductor,
photonics, sensors/MEMS and discrete semiconductor fabs.
o
Category 7: Display fabs covering OLED,
Micro LED and LCD technologies.
4.
Pillar 4 Strengthening ATMP/OSAT
o
Category 8: Semiconductor Assembly, Testing,
Marking & Packaging (ATMP) and Outsourced Semiconductor Assembly & Test
(OSAT) facilities, including advanced and legacy packaging.
5.
Pillar 5 R&D
o
Category 9: R&D for advanced
semiconductor technologies such as advanced CMOS fabrication, silicon
photonics, display fabrication and chiplet-based advanced packaging.
o
Government support can reach 75% of project cost,
including Capex and Opex and State incentives.
6.
Pillar 6 Talent Development
o
Category 10: Development of semiconductor
talent from undergraduate/postgraduate/doctoral levels to shop-floor
technicians and operators.
o
Support can reach 75% of project cost,
including Capex and Opex and State incentives.
Key
Financial Incentives
·
Commercial chip design:
Start-ups/MSMEs can receive seed funding up to ₹15 crore, with
milestone-linked support of 50% of project cost or ₹15 crore,
whichever is lower. Equity co-investment is also available where VC/PE
funding has been secured.
·
Deployment-linked incentive: Eligible
new IPs/chips/SoCs receive 9% reimbursement on net sales for five years,
capped at ₹30 crore per application and ₹120 crore per
company across multiple products.
·
Silicon wafer fabs: Minimum
investment of ₹20,000 crore, minimum revenue of ₹7,500
crore, with government support of 40% of eligible Capex.
·
Compound semiconductor/photonics/sensor fabs: Minimum
investment ₹500 crore, minimum revenue ₹200 crore,
with 35% of eligible Capex as government support.
·
Display fabs: Government support is 35% of
eligible Capex for eligible OLED, Micro LED and LCD projects. Investment
thresholds range from ₹1,500 crore for Micro LED to ₹10,000
crore for OLED/LCD.
·
ATMP/OSAT: Advanced packaging projects
receive 35% of eligible Capex, while legacy packaging receives 25%.
Both require minimum investment of ₹1,000 crore and minimum revenue of
₹200 crore.
Eligibility
& Strategic Conditions
·
Strategic semiconductor design projects require
companies incorporated and headquartered in India, with significant domestic
operations/manpower and ownership/control by Indian citizens.
·
Commercial design projects can be undertaken by
Indian-headquartered companies owned and controlled by Indian citizens or
OCIs.
·
Applicants may participate independently or through
consortia with global companies, R&D organisations and academic
institutions.
·
Strategic projects must comply with Government
rules on security, export controls and foreign acquisition/control. For
commercial design, IP rights and associated design/development files must
remain within India.
Implementation
& Approval
·
India Semiconductor Mission (ISM) will be
the Nodal Agency for Semicon 2.0, with C-DAC
assisting in the design/IP-related categories.
·
Applications will undergo technical and
financial appraisal, including assessment of process technology,
implementation capability, operational capability and offtake.
·
Approval hierarchy for semiconductor design and
talent-development projects:
o
Below ₹100 crore:
Secretary, MeitY
o
₹100500 crore:
Minister, MeitY
o
Above ₹500 crore: Cabinet
approval.
·
Projects under other categories are to be placed
before the Union Cabinet following ISM/MeitY
appraisal.
Duration
& Application Window
·
Individual projects may generally run for up to
six years, depending on the project.
·
The scheme will initially remain open for
applications for three years, with applications submitted through the
Nodal Agency's portal.
·
A mid-term impact assessment after three years
will determine whether the scheme should be continued or modified.
Overall significance: Semicon 2.0 moves beyond support for individual
semiconductor fabs to create an end-to-end domestic ecosystem covering
design → equipment/materials → wafer fabrication →
packaging/testing → advanced R&D → talent, with substantial
government fiscal support.