TSMC Explores Radical
New Chip Packaging Approach to Feed AI Boom
Rectangular
substrates to unlock more power are also being tested by Intel and Samsung
·
New
approach is to use rectangular panel-like substrates, rather than the conventional
round wafers used today, allowing more sets of chips to be placed on each wafer.
·
TSMC's
advanced chip stacking and assembly techniques -- used to produce AI chips for Nvidia,
AMD, Amazon and Google
·
Chip
packaging technology, once viewed as a relatively low-tech aspect of chipmaking,
has become increasingly important to maintaining the pace of semiconductor advancement.
·
Display
and PCB makers are specialists when it comes to handling rectangular substrates
Taiwan
Semiconductor Manufacturing Co. is exploring a new method of advanced chip packing
as the world's biggest chipmaker races to keep pace with the AI-fueled demand for computing power.
TSMC
is working with equipment and material suppliers on the new method, though commercialization
could take several years.
The
idea behind the new approach is to use rectangular panel-like
substrates, rather than the conventional round wafers used today, allowing more
sets of chips to be placed on each wafer.
The
study is still in its early stages, but it represents a significant technical shift
by TSMC, which previously viewed the use of rectangular substrates as too challenging.
To make the new method work, TSMC and its suppliers would have to devote a significant
amount of time and effort to development as well as upgrade or replace numerous
production tools and materials.
The
rectangular substrate currently in trials measures 510 millimeters
by 515 millimeters and has a usable area more than three
times bigger than that of round wafers. The rectangular shape means there would
also be less unused area left over at the edges, sources said.
TSMC's advanced chip stacking and assembly
techniques -- used to produce AI chips for Nvidia, AMD, Amazon and Google -- employ 12-inch silicon wafers, the largest
available. The chipmaker is expanding its advanced chip packaging capacity in Taiwan
to keep up with runaway demand. The expansion in Taichung is mainly for Nvidia,
sources briefed on the matter said, while its Tainan expansion is for Amazon and
Amazon's chip design partner Alchip.
Asked
for comment, TSMC said it "closely monitors progress and development in advanced
packaging, including panel-level packaging." The company said it does not comment
on individual customers.
For
AI computing chips like Nvidia's H200 and B200, using state-of-the-art chip production
alone is not enough. Advanced chip packaging technology called CoWoS, chip-on-wafer-on-substrate pioneered by TSMC, is also
necessary. For B200 chipsets, for example, CoWoS makes
it possible to combine two Blackwell graphic processing units and connect them with
eight high bandwidth memories (HBMs), enabling fast data throughput and accelerated
computing performance.
But
as chip size grows to accommodate more transistors and to integrate more memory,
the current industry standard -- 12-inch wafers with an area of approximately 70,685
sq. millimeters -- may not be efficient enough for packaging
cutting-edge chips in a couple of years.
For
example, only 16 sets of the B200 can be built on a single wafer, and that is assuming
the production yield is 100%, according to chip industry executives. About 29 sets
of the earlier H200 and H100 chips can be packaged on one wafer, according to an
estimate by Morgan Stanley.
"The
trend is certain. The size of the package will only grow bigger [as chipmakers]
squeeze more computing power out of chips used for AI data center
computing," one chip executive told Nikkei Asia. "But this is still at
an early stage. For example, the coating of photoresists in cutting-edge chip packaging
on a new shape of substrate is one of the bottlenecks. It takes the deep pockets
of chipmakers like TSMC to push equipment makers to change equipment designs."
Display and PCB makers are specialists when
it comes to handling rectangular substrates, but chip production demands a higher level of equipment and
material precision, industry executives and analysts said.
Mark
Li, a semiconductor analyst with Bernstein Research, said TSMC may need to consider
using rectangular substrates soon because AI chipsets are going to require ever
more chips per package.
"This
shift would require a significant overhaul of facilities, including upgrades to
robotic arms, and automated material handling systems to process the different shapes
of substrates," Li said. "This is likely a long-term plan spanning five
to 10 years, not something achievable in the short term."
Intel
is also working with suppliers to explore panel-level packaging, while Samsung,
which has expertise in display making, has also trialled new ways of packaging chips.
Some
companies, such as chip packaging and testing providers Powertech Technology have
invested in panel-level chip packaging technology. Display panel makers such as
BOE Technology Holding and Taiwan's Innolux are also allocating resources to developing
panel-level chip packaging technology as part of their efforts to diversify into
the semiconductor industry.